This application relates to integrated circuits such as programmable logic array integrated circuits (“programmable logic devices”), and more particularly, to ways in which to reduce power consumption of an integrated circuit.
Programmable logic devices (PLD) are integrated circuit devices where the logic elements may be customized by a user. A customized programmable logic device may be used to perform customized logic functions when the device is operated in a system. To customize a programmable logic device, the device is loaded with configuration information, also referred to as programming data. The programming data may be stored in a flash memory chip, disk drive, or other storage device in the system. Upon power-up, the programming data may be loaded from the flash memory chip or other storage device into configuration random-access memory (CRAM) cells on the programmable logic device. The output of each CRAM cell is either a logic high signal or a logic low signal, depending on the value of the programming data bit stored within the CRAM cell. The output signal from each CRAM cell may be used to control a corresponding circuit element. The circuit element may be, for example, a pass transistor, a transistor in a logic component, such as a multiplexer or demultiplexer, a transistor in a look-up table, or a transistor or other programmable circuit element in any suitable configurable logic circuit.
When the gate of an n-channel metal-oxide-semiconductor (NMOS) transistor that is controlled by a CRAM cell is driven high (because the CRAM cell contains a logic “one”), the transistor is turned on so that signals can pass between its drain and source terminals. When the gate of the transistor is driven low (because the CRAM cell contains a logic “zero”), the transistor is turned off. In this way, the transistors on the programmable logic device and therefore the functionality of the logic on the programmable logic device can be configured.
As the feature size of the transistors making up the integrated circuits is becoming smaller and smaller, leakage is becoming more of a problem, especially between the source and the drain of the corresponding transistors. Excessive leakage current from circuits may lead to a large standby power consumption rate. This large standby power consumption is undesirable as the trend is to reduce power consumption of the integrated circuit.
As a result, there is a need to solve the problems of the prior art to reduce the standby power consumption of an integrated circuit, especially as feature sizes continue to shrink.